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HW#17
Assign Mon 4/25
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 | Read Wakerly Chapter 7.3 (State Machine Analysis). Most important:
 | Draw the block diagram of a synchronous state machine (Mealy and
Moore). |
| Derive the characteristic equations of edge triggered D, T, and
J-K flip flops. |
| Analyze a given state machine logic diagram, producing
excitation equations, output equations, transition equations,
transition/output table, state/output table, and state diagram. |
|
| Work Wakerly problems 7.[2 through 8] (Latches and Flip-flops). Notes:
| Assume the initial state of the latches in the waveform
problems is zero. |
| P7.4 through P7.8 - when the problem statement says to
"show how", it means to draw the logic diagram, using the
proper logic symbols and bubble-to-bubble logic. |
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HW#16
Assign Mon 4/18 |
| Read Wakerly Chapter 7-7.2 (Bistable, Latches, Flip-Flops). Most important:
| Define: sequential circuit, state, finite state machine,
metastability. |
| Calculate the period, frequency, or duty cycle of a given clock
signal. |
| Draw symbols, function tables, internal logic diagrams, &
timing diagrams for all types of latches and flip-flops. |
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HW#15
Assign Wed 4/13
Due Mon 4/18 |
| Read Wakerly Chapter
5.10 through 5.10.6, skipping 5.10.4 (Adder, Subtractor,
and ALU) and 6-6.1 (Combinational Design Examples). Most important:
| Draw symbol, truth table, & internal logic diagram for a
generic full adder. |
| Draw logic diagram of a generic ripple-carry multibit adder/subtractor. |
| Draw the symbol & describe operation of: 74x283, 74x181. |
| Create a diagram for a larger adder or ALU based on using existing
smaller adders and ALUs. |
|
| Work Wakerly problems 5.[67, 68, 27, 29, 71, 75] (XOR, Parity,
Comparator). Notes:
| P5.71 and 5.75 - when the problem statement says to
"design", it means to draw the logic diagram, using the
proper symbols and bubble-to-bubble logic. |
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HW#14
Assign Wed 4/6
Due Mon 4/11 |
| Read Wakerly Chapter 5.8 through 5.8.4
(Exclusive OR/NOR and Parity) and 5.9 through 5.9.4 (Comparator). Most important:
| Define: XOR, XNOR, Parity Generator, Comparator, Magnitude
Comparator. |
| Draw symbol, truth table, & internal logic diagram for: XOR,
XNOR. |
| Draw the symbol & describe operation of: 74x280, Comparator,
74x85, 74x682. |
| Create a diagram for a larger magnitude comparator based on using existing
smaller magnitude comparators. |
|
| Work Wakerly problems 5.[22, 23, 54, 57(a,b,c)] (Multiplexers).
Notes:
| P5.22 and P5.23: More precisely, find the single worst-case
delay of the longest path, ignoring all transition directions.
Show your work, including the exact path chosen. |
| P5.57: Also give the truth table, in addition to the word
description, in part (b). |
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HW#13
Assign Wed 3/30
Due Wed 4/6 |
| Read Wakerly Chapter 5.6 through 5.6.2, skipping 5.6.3 and 5.6.4 (Three-state).
and 5.7 through 5.7.3, skipping 5.7.4 through 5.7.6 (Multiplexer
and Demultiplexer). Most important:
| Define: three-state device, multiplexer, demultiplexer. |
| Draw symbols for various three-state devices. |
| Draw symbol, truth table & logic diagram for: generic
multiplexer, 74x151, 74x153, 74x157. |
| Create a diagram for a larger multiplexer based on using existing
smaller multiplexers. |
|
| Work Wakerly problems 5.[20, 21, 45, 46, 48] (Encoders). Notes:
| P5.45: Draw a logic diagram for your design. |
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HW#12
Assign Wed 3/23
Due Wed 3/30 |
| Read Wakerly Chapter 5.5 through 5.5.2, skipping 5.5.3 and 5.5.4 (Encoders).
Most important:
| Define: encoder, binary encoder, priority encoder. |
| Draw symbol, truth table & logic diagram for: generic binary
encoder, generic binary priority encoder, 74x148. |
| Create a diagram for a larger encoder based on using existing
smaller encoders. |
|
| Work Wakerly problems 5.[16, 17, 18, 19(bcd), 35, 36] (Decoders and
Timing).
Notes:
| On all timing calculation problems, describe the circuit path
used and show each number in the calculation. |
| P5.19 - Use real 74x parts ONLY and include specific 74x part
numbers for all components used on the diagram. |
| P5.36 - The question "How can the cost..." is
rhetorical, so you don't need to answer it. Instead of 10 k-maps, you may
(if you wish) use a single k-map for all the SOP outputs in this
problem, if you write the decoded number (0-9) in the k-map
squares instead of the usual 1s, since the outputs are mutually
exclusive. You can use don't cares. |
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HW#11
Assign Wed 3/16
Due Wed 3/23 |
| Read Wakerly Chapter 5.4 through 5.4.5 and 5.4.8, skipping 5.4.6 and
5.4.7 (Decoders). Most important:
| Define: decoder, binary decoder. |
| Draw symbol, truth table & logic diagram for: generic binary
decoder, 74x139, and 74x138. |
| Create a diagram for a larger decoder based on using existing
smaller decoders. |
| Define purpose and usage of a seven segment decoder. |
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| Work Wakerly problems 5.[9, 10, 13, 14] (Timing). |
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HW#10
Assign Fri 3/4
Due Wed 3/16 |
| Read Wakerly Chapter 5.2 through 5.3.3 (Timing and PLDs). Most important:
| What is a timing diagram? |
| Draw a timing diagram, showing min/max specs. |
| Understand and use the delay tables 5-2, 5-3. |
| Understand the concept of programmable logic. |
| Describe the features of a particular programmable logic device
from its diagram. |
|
| Work Wakerly problems 5.[2-7] (Documentation). Notes:
| 5.2 - 5.3: Include part numbers and pin numbers. |
| 5.4 - 5.7: Explain your answers. |
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HW#9
Assign Fri 2/25
Due Fri 3/4 |
| Read Wakerly Chapter 4.3.6, 4.3.7, 5.1 (K-map POS, K-map don't-cares,
Design Documentation). Most important:
| Minimize to Product-of-Sums form using a K-map. |
| Minimize to SOP/POS with don't-cares in K-map. |
| List and define all the items in a system documentation package. |
| Describe the content of a block diagram. |
| Name signals according to their active level. |
| Draw bubble-to-bubble logic diagrams. |
| Draw a schematic diagram. |
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| Work Wakerly problems 4.[213 (acef), 214 (ef), 219 (ace), 220 (ac),
269 (bde), 270(e), 272 (bf), 274 (b)] (K-maps) . |
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HW#8
Assign Mon 2/21
Due Fri 2/25 |
| Read Wakerly Chapter 4.3.2 through 4.3.5 (Combinational Synthesis,
Karnaugh Maps). Most important:
| Convert And-Or diagram to Nand-Nand diagram. |
| Convert Or-And diagram to Nor-Nor diagram. |
| Define: circuit minimization, K-map. |
| Draw a Karnaugh Map (K-map) from a truth table or equation. |
| Minimize to Sum-of-Products form using a K-map. |
| Define: minimal sum, imply, include, cover, prime implicant,
prime implicant theorem, distinguished 1-cell, essential prime
implicant. |
|
| Work Homework #8 handout (Analysis
and Word Problems). |
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HW#7
Assign Wed 2/16
Due Mon 2/21 |
| Read Wakerly Chapter 4.2-4.3.1 (Combinational Analysis, Intro
to Synthesis). Most important:
| From a given logic diagram, derive any of the five standard
representations. |
| From a given logic diagram, directly derive its non-standard Boolean
equation; then convert it to SOP or POS form if required. |
| Convert a logic diagram containing Nand or Nor gates to another
form using And or Or gates. |
| Given a word description of a logic function, synthesize and
draw a logic diagram. |
|
| Work Wakerly problems 4.[205, 207(acegi), 209(cdf), 53] (Standard
Representations) . For problem 4.207, also express each function as a
minterm list and a maxterm list. |
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HW#6
Assign Wed 2/9
Due Wed 2/16 |
| Read Wakerly Chapter 4.1.5 through 4.1.6. (Duality and
Representations). Most important:
| Define: Duality Principle |
| Find the dual of a theorem or identity |
| Define: literal, product term, sum term, sum-of-products,
product-of-sums, normal term, minterm, maxterm |
| List and define the five standard logic representations. |
| Convert a Boolean equation into any of the five standard logic
representations. |
| Convert a logic function among any of the five standard logic
representations. |
|
| Work Wakerly problems 4.[2, 4(T8,T9), 29-32, 35, 206] (Boolean Algebra).
In all the problems, be
sure to indicate the particular axiom or theorem beside
each line of your proof (by placing the equation of the axiom or
theorem in parentheses), that justifies that step. Thus you must
derive each of the answers with one line per axiom or theorem
used. Don't skip steps! |
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HW#5
Assign Fri 2/4 |
| Read Wakerly Chapter 4 through 4.1.4 (Boolean/Switching Algebra
basics). Most important:
| Define: combinational vs. sequential circuit |
| Define: positive vs. negative logic convention |
| Use axioms, operators, and symbols: And, Or, Not |
| Use single-variable theorems |
| Use two/three-variable theorems |
| Use n-variable theorems |
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HW#4
Assign Wed 2/2
Due Mon 2/7 |
| Read Wakerly Chapter 2.10 through 2.13 (Codes). Most important:
| Define: code, code word, BCD, Gray code, ASCII |
| Why are these useful? BCD, Gray code, ASCII |
| Perform BCD addition and conversions |
|
| Work Homework #4 (Negative
Numbers and Signed Arithmetic) WITHOUT using a calculator. You must show
detailed work; answers alone are WRONG. |
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HW#3
Assign Fri 1/28
Due Wed 2/2 |
| Read Wakerly Chapter 2.6 through 2.9. (Signed Arithmetic). Most
important:
| Perform Two's complement add/subtract. |
| Convert the result to decimal. |
| What is "overflow" and 2 ways to detect it. |
| Perform unsigned binary shift/add multiplication. |
| How many bits can be in the product? |
| Perform unsigned binary shift/subtract division. |
|
| Work Wakerly problems 2.[1(abefij), 3(af), 5(aefij), 6(aij),
202(ae), 204, 207(ac), 208(ac), 210(ac)] (Number Systems and Unsigned
Arithmetic) WITHOUT using a calculator.
You must show detailed work using the methods in the textbook; answers alone are WRONG. |
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HW#2
Assign Mon 1/24
Due Wed 1/26 |
| Read Wakerly Chapter 2 through 2.5. (Number Systems and
Unsigned Arithmetic). |
| Work Wakerly problems 1.[2, 3, 7]. |
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HW#1
Assign Wed 1/19
Due Mon 1/24 |
| Read Wakerly Chapter 1 (Intro to Digital Systems). |
| Prepare a short autobiography, including both personal and
professional aspects of your life. You may email it to Dr.
Haggard at rhaggard@tntech.edu or bring a printed copy
to class. |
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