ECE 3110 - Intro to Digital Systems

Final Exam - Fall 2002

Rules: Closed book and notes. Any type of calculator is allowed (but not necessary). Show all your work for full credit, using the standard methods. Please draw and write NEATLY (If I cannot read it, I must mark it WRONG). Do all work and put all answers on YOUR paper, not this sheet. Give a single answer (enclosed in a box if it's a number, equation, or expression) to each question. Keep your work and the associated answer together, and carefully label them with the problem number and part number. Use only one side of the paper. Use the standard conventions and definitions that have been discussed in class.

 

1. [20 pts] Analyze this FSM circuit and supply the results as indicated below. Use the order "Q1 Q2" for the state codes, "S T" for the inputs, and "Y Z" for the outputs. Make it clear which answers go with which parts (a, b, c, or d).

  1. Minimal SOP Excitation equations
  2. Minimal SOP Output equations
  3. Minimal SOP Transition equations
  4. Transition/Output table

2. [10 pts] Draw a ladder logic diagram for a PLC that will implement this function. As always for PLCs, "on" means a contact is closed and "off" means a contact is open. Output Y1 will be on when B is on and either A is on or C is off. Output Y2 will be on when D is on, E is off, and F is on. Output Z1 will be on when either Y1 or Y2 is on.

3. [30 pts] Design a combinational logic circuit that performs the following function, and give the results specified in parts (a) and (b) below. All values are 7-bit unsigned binary numbers, with bits labeled 6 (MSB) down to 0 (LSB). The output Z is the maximum of 2 values, X and S, where X is an input and S is an internal signal which is calculated as the 7-bit sum of inputs A and B.

  1. Draw a proper, single-level, block diagram showing the structure of this system as a collection of interconnected function blocks and signals. Use one or more generic functions from this list: encoder, decoder, multiplexer, tri-state buffer, parity generator, comparator, adder, subtractor, ALU. No other types of function blocks or gates are allowed. Each function block in this block diagram can process any specific number of bits (unlike real MSI devices). Label every signal and block in the diagram. Be sure to label all bus signals with their bus size (e.g. Z[6..0]) and label all function block names with their bit sizes (e.g. 3-to-8 decoder, 5-bit 4-to-1 mux, 6-bit tri-state buffer, 9-bit ALU).
  2. Draw a schematic of this system, using a minimal number of standard 74xxx MSI devices that were discussed in this course. Refer to the attached list of symbols for these devices. Label all components with their part numbers and standard pin names, but omit pin numbers and unit numbers. All inactive or unused inputs should be tied either high or low, as appropriate, and not left floating. Be as neat as possible!

 

4. [25 pts] After studying the description of a logic problem involving 4 inputs (A,B,C,D), a TTU digital engineer determined that the function F  should be a logic one whenever this equation is true:

(A + B + C + D')' + A' · B · C' · D + ( (A' + B + D) · (B' + C + D') )' + A' · B' · (C' + C · D') = 1

She also decided that the value of F does not matter whenever this equation is true:

A' + B + D' = 0

Complete her design by giving the following results. Be sure to clearly show your work in the order that you performed it.

  1. Minterm list for F.
  2. Maxterm list for F.
  3. Minimal SOP equation for F.
  4. Minimal POS equation for F.

 

5. [15 pts] You must show all your calculation steps, by hand, for full credit on this problem.

  1. Convert the one's complement format binary number 010101.011 to its equivalent decimal value.
  2. Convert the signed decimal value -91.8 to its equivalent binary value, in the two's complement format, with a 10-bit integer part and the fractional part truncated to 3 bits.
  3. Convert the unsigned binary number 1100110 to its equivalent (a) Octal value and (b) Hexadecimal value.