Rot13 Encryption Project
Revision History:
 | 4/6/05 Original version. |
| 4/14/05 Deleted requirement for multi-page
hierarchical block diagram in Phase 1 Requirements. |
Table of Contents
Each team will design and evaluate a combinational logic circuit for
a rot13 encryption/decryption system, under several constraints, to satisfy certain
requirements.
| W 4/6 Request Groups |
| F 4/8 Groups confirmed, Project assigned |
| M 4/11 |
| M 4/18 Phase 1 - System Design & Progress Check |
| M 4/25 Phase 2 - Detailed Design and Final Report |
| Each member must clearly design at least one section of the project. |
| Essential to generously help each other within each team, but
still allow each member to do their own work. |
| With each phase, turn in a private, signed evaluation of your team members
(including yourself) regarding
their level of cooperation and contributions to the project. Include a numeric score from 1
(totally uncooperative and non-contributing) to 10 (fully cooperative and contributing
their share of the work) as well as justification of this score. Also, list specifically, in detail, what work
you performed
during the phase and how many hours you worked. Part of each student's grade
depends on this team evaluation. |
| No discussion BETWEEN teams. |
| Project Grade consists of
 | Proper functionality and results (meets the required specs exactly): 30% |
| Clear, professional documentation (correct design procedure, complete,
logical development using proper English, and high-quality
figures): 60% |
| Good teamwork and cooperation: 10%. |
|
| All the text material for the report should be written with MS
Word in a consistent format. Block diagrams, schematics, K-maps,
etc. may be carefully hand drawn on engineering paper OR
created in a graphical program such as Visio or Altera Quartus, if
you prefer. All computer-based work must be saved in your team's shared network
directory, under \phase*\. For example, Team1 will save their final phase2 work under
\\digital5\3110team1$\phase2\. |
| The primary design goal is proper functionality. The secondary
design goals are minimal cost and propagation delay. |
| rot13 /rot ther'teen/ n.,v.
[Usenet: from `rotate alphabet 13 places'] The simple Caesar-cypher encryption that replaces each English letter with the one 13 places forward or back along the alphabet, so that "The butler did it!" becomes "Gur ohgyre qvq vg!" Most Usenet news reading and posting programs include a rot13 feature. It is used to enclose the text in a sealed wrapper that the reader must choose to open -- e.g., for posting things that might offend some readers, or spoilers. A major advantage of rot13 over rot(N) for other N is that it is self-inverse, so the same code can be used for encoding and decoding. |
| For further details and examples of rot13, see:
|
| Your system should accept a 7-bit ASCII character, plus an enable
bit, and output the rot13 encoded/decoded 7-bit ASCII character, as
long as the enable is true. If the enable is false, the input
character should be passed to the output without any changes. |
| This is the high-level system design, without all the
implementation details. |
| Contents in order:
| Title Page with project
title, phase number with description, TTU class number and
title,
date of submission, team name, team number, and member list. |
| Table of Contents (TOC) with section titles and page numbers.
Make sure that there are page numbers on every page of the
document (except Title and TOC). |
| A copy of this Guideline document. |
| Design Choices, including any choices you
made that were not given in the spec (input/output signal name
definitions, bit order definitions, unused or special codes,
calculation methods, and description of how it works (related to the
block diagram). |
| Detailed block diagram (graphic). |
|
| Block diagram blocks must ultimately be refined to standard MSI-type
functions or special-purpose gate-level functions which you can minimize with
K-maps or Boolean algebra. NO GATES or MSI components allowed are allowed in
the block diagram, only functions. The block diagram will be flat,
since it should fit on one page. Examples of MSI-type functions include n-to-m decoders,
m-to-n encoders, m-bit n-to-1 multiplexers, n-bit adders, etc. Any
function that is not based on a standard MSI function is a special
purpose gate-level function. |
| Each block must have a descriptive function name (e.g. "code_output_mux"), not
just a number (e.g. "block2"). |
| Name each signal line with the signal name (e.g. "select4"), NOT
its source or destination (e.g. "from adder block" or "to
multiplexer"). |
| The report needs to be a coordinated, organized document with everything
working together, as though one person wrote the entire document. It should
NOT look like it was thrown together by 4 people who never talked to each
other! Thus use consistent style, fonts, indentations, names, structures,
etc. |
| Complete the detailed system design and produce the Final Report.
Include the revised sections from Phase1 plus the new material. |
| Contents in order:
| Title Page |
| Table of Contents |
| A copy of this Guideline document |
| Design Choices |
| Detailed block diagram |
| Schematic, which may be flat or hierarchical (if
necessary). Draw a proper bubble-to-bubble hierarchical schematic of
the complete circuit. This is an SSI\MSI level design, so it will
contain only SSI gates and standard MSI components.
Recall that a schematic must include real part numbers for the ICs,
correct pin numbers, and reference (unit) designators. Page 329
(Figure 5-18) of Wakerly gives the pinouts of all the standard SSI
gates that may be used. Elsewhere in Wakerly chapter 5 are details
of all the MSI components that may be used. Use the 74HCT family of ICs. |
| Max Propagation Delay. Calculate the longest propagation delay from any input to any
output of this system using the "worst case" method given
in Wakerly, ignoring specific transitions, but including the
specific path. Use the timing specs given on pages 334-335 (Tables
5-2 and 5-3)
in Wakerly. Also specify the corresponding longest path through the
circuit that gives this worst case delay. |
| Parts List and Cost. Calculate the cost based ONLY on the cost of all the
ICs, assuming the use of DIP packages and quantities of 100,
from vendor Digi-Key at http://www.digi-key.com/.
Obviously, this ignores many other costs, such as labor, overhead,
the PWB, capacitors, resistors, sockets, connectors, etc. |
| Design work details: truth tables, logic equations, K-maps,
Boolean algebra, etc., for all special-purpose gate-level
blocks. Everything should be readable, well-organized, clearly labeled,
and related to the corresponding schematic and block diagram
items. |
|
Common errors that can cause reductions in grade:
| Wrong or missing subdirectory name in your team directory. |
| Omitting
ratings or justifications in the separate private member evaluation sheets. |
| Missing some of the required information. |
| Wrong or missing page numbers in the TOC or on other pages in the
report. |
| Insufficient detail in the TOC. |
| Block Diagram and Schematic errors: non-functional (does not meet all or some of the
specs), too complex (poor design), missing signal names, mismatched
signal names, not using buses where appropriate, missing #bits on buses,
duplicate block names on different blocks (they must be unique), poor
functional names for blocks, showing individual gates on block diagram, failing to
decompose complex blocks into simple blocks, logical design
errors, omitting details like adder size, using the same
name for blocks and signals. |
| Poor English grammar and spelling, confusing or messy report
layout, or messy drawings.
You should write this as though it were an English class assignment. |
|
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