HW#17
Assign Mon 11/26
Due Wed 12/5 |
- Work the Homework# 17 handout (Combo
System Design - Part 3).
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HW#16
Assign Mon 11/19
Due Mon 11/26 |
- Work the Homework# 16 handout ( FSM Design - Manual Implementation).
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HW#15
Assign Wed 11/14
Due Mon 11/19 |
- Read Wakerly sections 8.1, 8.2, 8.4, 8.5 (Sequential
timing, registers, counters, shift registers). Skip AHDL and
Verilog
sections 8.2.6, 8.2.8, 8.4.5, 8.4.7, 8.5.7, and 8.5.9.
- Work the Homework# 15
handout (VHDL State Machine Implementation).
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HW#14
Assign Fri 11/9
Due Wed 11/14 |
- Read Wakerly sections 7.12 - 7.12.4 (Sequential VHDL - FSM).
- Work the Homework# 14 handout (FSM Analysis and Design).
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HW#13
Assign Fri 11/2
Due Fri 11/9 |
- Read Wakerly section 7.4 (FSM Design).
- Work the Homework #13 handout
(Combo System Design - Part 2)
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HW#12
Assign Fri 10/26
Due Mon 10/29
& Fri 11/2  |
- Work the Homework #12 handout
(Combo System Design - Part 1)
|
HW#11
Assign Wed 10/24
|
- Review Wakerly sections 7.1 - 7.3 (Flip-Flops and FSM
Analysis).
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HW#10
Assign Fri 10/19
Due Fri 10/26 |
- Read Wakerly sections 6-6.1.1 (Design Practices).
- Work the Homework #10 handout (VHDL
Analysis).
|
HW#9
Assign Fri 10/12
Due Fri 10/19 |
- Read Wakerly sections 6.4.6, 6.7.5, 6.9.7,
6.10.9, (VHDL standard MSI functions).
- Work the Homework #9 handout (Combinational VHDL Design:
Behavioral).
|
HW#8
Assign Fri 10/5
Due Wed 10/10 |
- Read Wakerly section 5.3.7 (VHDL Behavioral model).
- Work the Homework #8 handout
(VHDL - Quartus Simulation and Implementation).
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HW#7
Assign Mon 10/1
Due Fri 10/5 |
- Become familiar with Altera Quartus and its Online Help:
- Contents
- Tutorial - Interactive (esp. Modules 1,2,5)
- PDF Tutorial for VHDL Users
- Note: See our References page to
download your own free copy of Quartus.
- Work the Homework #7 handout
(Dataflow VHDL).
|
HW#6
Assign Wed 9/26
Due Mon 10/1 |
- Read Wakerly section 5.3.6 (VHDL Dataflow model).
- Work the Homework #6 handout
(Structural VHDL).
|
HW#5
Assign Wed 9/19
Due Mon 9/24 |
- Read Wakerly section 5.3.4-5.3.5 (VHDL Libraries, Structural VHDL
model).
- Work the Homework #5 handout
(VHDL Basics).
|
HW#4
Assign Fri 9/14
Due Mon 9/17 |
- Read Wakerly section 5-5.1, 5.3-5.3.2 (VHDL Intro, Structure, Types).
- Work the Homework #4 handout (PLD
comparisons).
|
HW#3
Assign Mon 9/10 |
- Read the Altera partial datasheet handouts, specifically the Features, General
Description, and Functional Description sections, for these two devices or families.
The complete documents are also available on the web:
|
HW#2
Assign Fri 8/31
Due Fri 9/7 |
- Read Wakerly Sections 9.5 and 9.6 (CPLDs, FPGAs).
- Work the Homework #2 handout (PLD
Functions).
|
HW#1
Assign Mon 8/27
Due Wed 8/29 |
- Review ECE 3110 prerequisite topics
(Wakerly
chapters 2, 4, & 6):
- Binary/hex number systems
- Boolean algebra, logic representations
- Standard MSI functions and usage
- Read Wakerly sections 6.3 and 8.3 (Combinational and Sequential PLDs).
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