ECE 4110 Homework

HW#16 Assign Mon 11/30 Due Fri 12/4	Read Wakerly sections 8.1, 8.2, 8.4, 8.5 (Sequential timing, registers, counters, shift registers). Skip the AHDL and Verilog sections 8.2.6, 8.2.8, 8.4.5, 8.4.7, 8.5.7, 8.5.9. Some important ideas you should learn: Define "synchronous system". What is a "dynamic indicator" on a logic symbol? List all the representations of state machines that we have discussed. State the two equations needed to verify the proper timing in a synchronous system. What is "switch contact bounce" and why is it a problem? What is a "register"? What is a "synchronous parallel counter"? What conditions cause the RCO output to be asserted in a 74x163? What is a shift register? What are the four classes or types of shift registers? What type of shift register is the 74x194? Describe the four functions that may be selected in the 74x194. What are the three major types of shift register counters? Describe the pattern of outputs produced by each type of shift register counter. What problem is fixed in a self-correcting counter? Write the VHDL for a specific type of shift register or shift register counter. Work the Homework# 16 handout (VHDL State Machine Implementation).
HW#15 Assign Mon 11/23 Due Mon 11/30	Read Wakerly sections 7.12 - 7.12.4 (Sequential VHDL - FSM). Work the Homework# 15 handout (FSM Manual Design).
HW#14 Assign Mon 11/16 Due Mon 11/23	Work the Homework #14 handout (Combo System Design - Part 3)
HW#13 Assign Fri 11/13	Read Wakerly section 7.4 (FSM Design). Some important ideas you should learn: List the 9-step manual FSM design process. What is the most important and creative step? Why? Why do you want to minimize the number of states? Why does the state assignment matter? What information exists in the transition/output table? How does it differ from the state/output table? What information exists in the excitation table? How do you determine the next state equations? How do you determine the output equations?
HW#12 Assign Wed 11/11 Due Fri 11/13	Work the Homework #12 handout (Combo System Design - Part 2)
HW#11 Assign Wed 11/4 Due Fri 11/6	Review Wakerly sections 7.1 - 7.3 (Flip-Flops and FSM Analysis). Some important ideas you should recall: What is the difference between a combinational and a sequential circuit? Give an everyday example of a sequential device. What is "state"? What are the states for your example device? What is a feedback sequential circuit? What is a clocked synchronous state machine? What is metastability? What causes it? What is the difference between a latch and a flip-flop? Give the function table and a sample timing diagram for: an S-R latch, a D-latch, and a D flip-flop. Draw block diagrams of a Mealy machine and a Moore machine (non-pipelined). Give the characteristic equation for a D flip-flop. List the seven steps for analyzing a state machine. Work the Homework #11 handout (Combo System Design - Part 1)
HW#10 Assign Fri 10/30 Due Wed 11/4	Read Wakerly sections 6-6.1.1 (Design Practices). Some important ideas you should learn: What is the key to creating a complex system? List and describe the six common types of documents needed for a digital system. What are the major elements shown in a digital system block diagram? How do you indicate a bus on a block diagram? In what direction should signals generally flow on a block diagram or schematic? Work the Homework #10 handout (VHDL Analysis).
HW#9 Assign Mon 10/26 Due Fri 10/30	Read Wakerly sections 6.4.6, 6.7.5, 6.9.7, 6.10.9, (VHDL standard MSI functions). Some important ideas you should learn: Which VHDL model for a decoder is the best one? Why? A multiplexer is modeled most easily with what kind of VHDL statement? How do you determine if a VHDL comparator is suitable for signed or unsigned numbers? What does the VHDL expression SIGNED(x) mean? Work the Homework #9 handout (Combinational VHDL Design: Behavioral).
HW#8 Assign Fri 10/16 Due Fri 10/23	Read Wakerly section 5.3.7 (VHDL Behavioral model). Some important ideas you should learn: What are the 3 types of sequential statements used in a process for a behavioral model (in this course)? Give a specific simple example of each type. What types of sequential statements are NOT used in this course? What is a PROCESS? Exactly WHEN does a process execute? Is the sensitivity list required for a process? The sequential IF statement is similar to which concurrent statement? The sequential CASE statement is similar to which concurrent statement? What is the restriction on the set of choices in a CASE statement? Work the Homework #8 handout (VHDL - Quartus Simulation and Implementation).
HW#7 Assign Mon 10/5 ~~Due Fri 10/9~~ Due Wed 10/14	Become familiar with Altera Quartus and its Online Help: Contents Tutorial - Interactive (esp. Modules 1,2,5) PDF Tutorial for VHDL Users Note: See our References page to download your own free copy of Quartus. Work the Homework #7 handout (Dataflow VHDL).
HW#6 Assign Wed 9/30 Due Mon 10/5	Work the Homework #6 handout (Structural VHDL).
HW#5 Assign Wed 9/23 Due Wed 9/30	Read Wakerly section 5.3.5-5.3.6 (Structural and Dataflow VHDL models). Some important ideas you should learn: Define Structural VHDL, component, instantiation, port map. How does instantiation differ from a conventional subroutine call in a HLL like C? Why would you use a generate statement? Or a generic constant? Give an example of both. What are the 3 types of concurrent signal-assignment statements used in dataflow models? Give a specific simple example of each type. What is the important rule regarding the set of conditions that appear in any concurrent conditional signal assignment (CCSA)? Give a specific simple example of a CCSA statement. What does the vertical bar symbol and the 'others' keyword mean in a concurrent selected signal assignment (CSSA)? Give a specific simple example of a CSSA statement. Work the Homework #5 handout (VHDL Basics).
HW#4 Assign Fri 9/18 Due Wed 9/23	Read Wakerly section 5-5.1, 5.3-5.3.2, 5.3.4 (VHDL Intro, Structure, Types, Libraries). Some important ideas you should learn: What traditional digital design tool has mostly been replaced by HDLs? What are the three HDLs covered in our book? What individual tools are typically included in an HDL design tool suite? What are the sequential steps in an HDL design flow? List the various standard versions of VHDL. What are the two major sections in a VHDL program? How do you indicate comments in VHDL? What is the purpose of an entity? What is the purpose of an architecture? List some of the predefined signal types. Declare examples of a signal and a constant. What library is automatically included in every VHDL design? What is in this library? How does a package differ from an entity/architecture? When would you want to create and use a package? Work the Homework #4 handout (Programmable Logic Comparisons).
HW#3 Assign Mon 9/14	Read the Altera partial datasheet handouts, specifically the Features, General Description, and Functional Description sections. The complete documents are also available on the web: Max7000 Family at Max7000_dsm7k04.pdf Flex10k Family at Flex10k_dsf10k02.pdf Some important ideas you should learn: Compare/contrast the Altera features and flexibility to the Xilinx CPLD/FPGA devices we have studied. Consider the Max7000 familiy: Is it a PLD, CPLD, or FPGA? Is the configuration electrically erasable (EEPLD) or UV erasable (EPLD)? What are the input/output dimensions of the internal PLDs (called LABs by Altera)? What is the full name and purpose of the PIA? What is the purpose of the I/O Control Blocks? What special purpose input pins are available? How many macrocells are in the biggest device? How many terms go to each macrocell, ignoring any sharing of terms? What does the Product Term Select Matrix do? What are the two ways of sharing terms between macrocells? Consider the Flex10k family: Is it a PLD, CPLD, or FPGA? Is it configured as EEPLD or EPLD? Define the acronyms IOE, EAB, LAB, LE. Describe the purpose and/or structure of each of the previous items. Where does RAM/ROM memory exist in the structure? What structure is very similar to a small PLD? What structure is very similar to a XIlinx CLB? Are there any flip-flops in the IOE or LE or EAB?
HW#2 Assign Fri 9/4 Due Fri 9/11	Read Wakerly Sections 9.5 and 9.6 (CPLDs, FPGAs). Some important ideas you should learn: Why is the CPLD structure superior to the PAL/GAL structure for larger devices? Use a numerical comparison. What are the input/output dimensions of the internal PLDs (called "function blocks" by Xilinx) in the XC9500 CPLD? How many global clock input pins are available in the XC9500? Describe the overall purpose of the product term allocators in the XC9500 macrocell. Describe the purpose of each component in the XC9500 macrocell and I/O block. Describe the overall structure of the XC4000 FPGAs. Describe the purpose of each component in the XC4000 CLB and IOB. What is the Programmable Interconnect in the XC4000? What does it contain and what is its purpose? Work the Homework #2 handout (PLD Functions).
HW#1 Assign Mon 8/31	If necessary, review ECE 2110 prerequisite topics. Read Wakerly sections 6.3 and 8.3 (Combinational and Sequential PLDs). Some important ideas you should learn: Name the five general classes of logic implementations. What distinguishes them? Draw the compact representation diagram of a 3 input, 2 output, 6 product term PLA. How do you produce a constant 0 or 1 term in a PLA or PAL? How does a PAL differ from a PLA? Draw the compact representation diagram of a 3 input, 2 output, 4 terms per output, PAL. What distinguishes a GAL from a PAL? Describe the basic structure of a CPLD and an FPGA. Define the acronyms: PLD, PLA, PAL, GAL, CPLD, FPGA. Name the different kinds of circuits and programming techniques used in all types of PLDs. What is a JTAG port? What single feature added to a combinational PLD makes it a sequential PLD? What features make a 22v10 much more versatile than a 20v8? How does each PLD timing spec affect the overall system logic design and its capabilities?