Homework

HW#13 Assign Mon 4/27 Due Fri 5/1	Work Homework #13 handout (Fixed Point multiply/divide, Floating Point numbers and calculations). This WILL BE collected, reviewed, and graded in class on Friday.
HW#12 Assign Fri 4/17 Due Wed 4/22	Read Heuring Chapter 6.4 (Floating Point Arithmetic). These topics will be covered in class somewhat differently than in the text book. Some important ideas you should learn: Analyze the IEEE single-precision binary floating point number format, and convert numbers to/from decimal format. Perform add/subtract/multipy/divide of floating point binary numbers. Analyze and/or design IEEE floating point binary adder, subtractor, multiplier, and divider hardware. Work the Homework #12 handout (Fixed Point Arithmetic).
HW#11 Assign Mon 4/6 ~~Due Mon 4/13~~ ~~Due Wed 4/15~~ Due Fri 4/17	Read Heuring Chapter 6.2 (Fixed Point Arithmetic). These topics will be covered in class somewhat differently than in the text book. The following text book topics will NOT be covered in class (so you are not responsible for them): 6.2.2 topic: Signed Multiplication, Booth Recoding 6.2.3 topic: Restoring/Nonrestoring Division and Array Divider Some important ideas you should learn: Write the equations and/or draw the logic diagram of a fixed point binary 2's complement ripple carry adder/subtractor. Write the equations and/or draw the logic diagram of a fixed point binary 2's complement Carry Lookahead Adder/Subtractor. Compare the delay times of ripple carry vs. carry lookahead methods. Analyze or design a sequential/iterative multiplier or array/direct multiplier for unsigned fixed point binary numbers. Analyze or design a sequential/iterative divider for unsigned fixed point binary numbers. Work these problems in Heuring Chapter 4: P4.13: As the problem says, revise the register file logic diagram from 1 port to 2 ports and also make it properly synchronous as was shown in class. Include the IR decoding logic similar to that used in the textbook Figure 4.4. P4.13x: Same as P4.13, but change to the 3-bus version (3-port register file). Only the Bbus needs to be driven as a result of the BAout control signal. P4.16: Base this problem on this specific 1-bus solution for NEG, using our synchronous classroom version of the system and its control signals. Assume the Zero-out signal drives a 32-bit zero value onto the Bbus in the 2-bus design and onto the Abus in the 3-bus design. Keep MA as a synchronous register, NOT a latch, in all versions. P4.16x: Using the results of P4.16, calculate the speedups of this NEG instruction on the 2-bus and 3-bus versions compared to the 1-bus version, assuming the combinational delay increases by 15% (for both new versions) over the 1-bus version. Show your formulas and all work. In all problems, state your assumptions, if any, beyond what is given in the textbook and define any new control signals that you must create.
HW#10 Assign Mon 3/30 Due Fri 4/3	Read Heuring Chapter 4.5 through 4.6 (SRC Control Unit and 2,3-Bus SRC). The Step Generator Control Unit in Section 4.5 will NOT be covered in detail and you will not be responsible for it. We will cover an alternative FSM Control Unit design in class, which you ARE responsible for. Some important ideas you should learn: How can you calculate the minimum clock period in our fully synchronous system (which differs from the level-sensitive latch timing discussed in the book)? Generally, how does increasing the number of buses speedup system operation? What factors will tend to reduce the net speedup? In what ways does the hardware complexity increase when changing from the 1-bus SRC to the 2-bus SRC? From the 2-bus to the 3-bus SRC? In what ways does the hardware complexity actually decrease when changing from the 1-bus SRC to the 2-bus SRC? From the 2-bus to the 3-bus SRC? Calculate the speedup from the 1-bus SRC to the 2-bus SRC. Calculate the speedup from the 1-bus SRC to the 3-bus SRC. Revise the concrete RTN and control sequences for any SRC instruction as needed for the new 2-bus or 3-bus SRC architectures. A. Work Heuring problems 4.[4,7]. Notes: You may omit the common instruction fetch steps, T0-T2, and start your answers with T3. You may enhance the architecture by adding bus sources for special constants if needed; but be sure to describe any such architectural changes and any new control signals. Use our corrected synchronous classroom version of the system and its control signals, e.g. memory signals (e.g. omit the wait), GotoT0, etc. 4.4: As the problem says, you must use the existing set of ALU operations only (no new ALU operations). 4.7: As the problem says, you must use the existing set of ALU operations only, EXCLUDING the NEG operation, and without adding any new ALU operations. B. Write a partial state transition/output list for the SRC controller, implemented as an FSM, for the addi, st, and shr instructions (including the common instruction fetch) using the 1-bus datapath. As always, minimize the number of states. As in part A, use our corrected synchronous classroom version of the system and its control signals.
HW#9 Assign Mon 3/23 ~~Due Mon 3/30~~ Due Fri 3/27	Read Heuring Chapter 4.3 through 4.4 (1-Bus SRC Datapath Implementation). Some important ideas you should learn: Why are we using only edge-triggered flip-flops, not level-sensitive latches, in our design? Why is our system designed to be fully synchronous (differing from the textbook)? List the control and status signals that are added to the original block diagram in section 4.4.1. Define the purpose of each signal (modified to be fully synchronous). List and define the control and status signals that are added to each of these datapath blocks: Register File, Instruction Register, Memory Interface, ALU. Add appropriate control sequences to the concrete RTN for any specific SRC instruction (or any other instruction). Work Heuring problems 4.[1,2,3]. Notes: For all these problems, you may omit the common instruction fetch steps, T0-T2, and start your answers with T3. Make sure that all of your concrete RTN can actually be accomplished in each clock cycle, using only the existing datapath and ALU operations (unless certain additions are allowed in a specific problem). 4.1: Do the la and str instructions as stated in this problem, even though the textbook errata sheet says to do the la and shr instructions. Also, first write the abstract RTN before developing the concrete RTN, for each part. 4.3: As the problem says, you must use the existing set of ALU operations only (no new operations). But you may enhance the architecture by adding bus sources for special constants if needed; you must clearly describe any such architectural changes.
HW#8 Assign Wed 3/18 ~~Due Wed 3/25~~ Due Mon 3/23	Read Heuring Chapter 4 through 4.2 (1-Bus SRC Microarchitecture). Some important ideas you should learn: Which "view" of a computer system is prevalent in Chapter 4? The abstract RTN of Chapter 2 is converted to what notation used in Chapter 4? What is a microarchitecture? What is the relationship between a "step" and a clock cycle? For the one-bus microarchitecture, how many steps are needed for the instruction fetch phase of instruction execution? For the one-bus microarchitecture, how many steps are needed for the remaining phases of instruction execution? Write the concrete RTN for any specific SRC instruction (or any other instruction) on the one-bus microarchitecture. Work Heuring problems 2.[21,22,24,27(a),28,29]. Notes: 2.21: The new instruction's RTN should NOT require any new registers and it should not use any memory locations. 2.24: "Autoincrement" should be "Auto-Post-Increment"; "Autodecrement" should be "Auto-Pre-Decrement". 2.27(a),28,29: Use the particular form of block diagrams, timing diagrams, and control signals that we discussed in class for proper synchronous systems.
HW#7 Assign Fri 2/27 Due Wed 3/4	Read Heuring Chapter 2.4 through 2.6 (SRC RTN). Some important ideas you should learn: Define the RTN symbols and their meanings. Understand the SRC instruction set as expressed in RTN, specifically registers and memory, register formats, address calculations, instruction interpretation, and instruction execution in the Move, ALU, and Branch categories Write RTN for any specified instruction set. Draw a logic diagram for basic RTN, using registers, buses, and multiplexers. Differentiate among abstract RTN, concrete RTN, and control sequences. Work the Homework #7 handout (SRC Assembly Language Code).
HW#6 Assign Mon 2/23 Due Fri 2/27	Work Heuring problems 2.[1,6,9,11,12] (Computer classes and Instruction formats). Notes: 2.1: Correct the instructions to say: Refer to the four items on page 35 that an instruction must specify. What exactly is specified for each item and is it specified explicitly or implicitly, by the MC68000 instruction ADDI.W #9,D4 as described in Table 1.2? 2.6 and 2.9: For each machine class, (a) write the shortest code to solve the problem, determine the memory traffic in bytes for (b) instruction fetch, (c)instruction execution, and (d) total, for each instruction and (e) the grand totals for all instructions in the program. Show how you got each number. 2.12: Also state what exactly is the value or meaning of each item for each instruction.
HW#5 Assign Wed 2/11 Due Wed 2/18	Read Heuring Chapter 2 through 2.3 (Computer Types and Instruction Sets, SRC Instruction Set). Some important ideas you should learn: Define the acronyms SRC and RTN. Discuss the pros and cons of an "accumulator machine". What is a "stack machine"? What is a "general register machine"? What information must be specified in every machine instruction? What are the meanings of the instructions "lwz R3,A", "nabs r3,r1", and "beq $2,$1,32"? What are the most common condition-code bits and meanings? What is specified explicitly in a 4-address machine? in a 3-address machine? in a 2-address machine? in a 1-address machine? Explain each of the common address modes shown in Fig. 2.9. Draw a diagram of the SRC register set and memory. Describe the instruction format and meaning of any given SRC instruction. Write the SRC instruction that reads a word from memory, addressed by the contents of register 2 plus 14, and stores it into register 5. Write the SRC instruction that performs the logical AND of the contents of register 7 and the value 13 and puts the result in register 12. Write the SRC instruction that jumps to the address contained in register 10 if the contents of register 22 is not zero. Work Heuring problems 1.[1,8,13,16,17,21,24,25] (Computer Views and History). Notes: 1.1: It will be easiest to do the calculations using powers of 2, like 2^x. Give the answer in two forms, as a power of 2 and as a decimal integer.
HW#4 Assign Wed 2/4	Read Heuring Chapter 1 (Computer Overview and History). Some important ideas you should learn: List and define the four "views" of a computer system. What is each concerned with? What does GB (gigabyte) usually mean? What does it mean for disk sizes? What is the "stored program concept"? List the steps in the instruction fetch-execute cycle. What is an ISA? What is "machine state"? What are the pros/cons of HLL versus Assembly Language? Discuss the "memory hierarchy". What "implementation domain" are we using in this class? List all the important pioneers who worked on computer systems up through the first generation of computers.
HW#3 Assign Fri 1/30 Due Wed 2/4	Work the Homework #3 problem set (ROM/SRAM).
HW#2 Assign Fri 1/23 Due Fri 1/30	Read Wakerly Chapter 9.1-9.4 (Memory), but skip 9.1.6. Some important ideas you should learn: How can ROMs be used in addition to its normal function as computer storage of programs and/or data? Draw a block diagram of a ROM organized using two-dimensional decoding. Why are ROMs usually organized this way? Give the names and features of all the ROM types discussed here. Analyze or draw a schematic of a microprocessor system using multiple ROMs of any type/size. Define and discuss the meaning of all the ROM or static RAM timing parameters. Give the names and features of all the RWM types discussed here. Which memory types are volatile and which are nonvolatile? For a static RAM cell, draw its logic diagram and discuss its operation. Discuss the internal block diagram of an NxM static RAM. Draw and discuss the block diagram of an SSRAM. For a DRAM cell, draw its schematic and explain its operation. Why is refresh cycle needed in a DRAM system? Discuss the internal block diagram of an NxM SDRAM. Discuss the SDRAM read and write cycles. What is the idea behind DDR SDRAMs? Work Wakerly problems 8.[19, 20, 83, 84] (Synchronous Systems, Metastability). For all problems, use at least 6 significant digits throughout the calculations and 3 significant digits in the answers; also give each of the MTBF answers in 3 forms, in units of seconds, days, and years. Notes: 8.19 Change the clock frequency from 25 to 90 MHz. Use the 1997 version in the table, not the 1983 version.
HW#1 Assign Thu 1/15	Read Wakerly sections 8.7 - 8.9.6 (Clocking and Asynchronous Interface). Some important ideas you should learn: What special requirements do synchronous systems place on the flip-flop clock, preset, and clear inputs? Why are races and hazards NOT a problem in a synchronous system? List the three designer tasks needed to ensure reliable synchronous system operation. Actually there is a fourth task; what is it? What are the two primary parts of a synchronous system? What kinds of functional components are typically used in a control unit? in a data unit? Explain the synchronous system structure shown in Fig. 8-63. Draw a timing diagram showing one clock cycle in a general synchronous system, label the important time periods, and write the equations for setup time margin and hold time margin. What causes clock skew? Why is it a problem? How can it be minimized? Why might you gate a clock? What problem is caused by bad clock gating? How can it be fixed? What is an asynchronous input? What problem does it cause? How do you fix it? Calculate the MTBF for a specified synchronizer (dual flip-flop, multi-cycle, or cascaded synchronizer type) in a system.