9/16/08 RLH
| Features to Learn and Use | Features to Omit - Not Required |
|---|---|
| VHDL-93 Entity/Architecture Ports Signals and Modes Lexical - Comments, Identifiers Types - Predefined - integer, string, bit string Types - Enumerated - boolean, character, std_logic Types - User Defined Array - std_logic_vector Array - Slice, Concatenation Constant Library, Use, Package Positional and Named Association Operators - logical, relational, arithmetic Models - Structural, Dataflow, Behavioral (S) Component Declaration, Instantiation (S) Generic, Generate (D) Concurrent Statements: Simple Signal Assignment Conditional Signal Assignment Selected Signal Assignment (B) Process (B) Sequential Statements: Simple Signal Assignment If-Then-Else Case |
VHDL-87 Variables Types - Access, File, Physical Types - Predefined - real, time, severity-level Types - Enumerated - bit, std_ulogic Subtypes Records Attributes (most) Functions Procedures Test bench Reject, Inertial, Transport Assert, Report After, Wait (S) Loop, For Loop, While Loop (S) Exit, Next |
Note: (S)=Structural, (D)=Dataflow, (B)=Behavioral Models