Dr. Roger L. Haggard

Altera UP1/2 University Board
Max7128 CPLD Pinout
 

Board Signal

EPM7128 Pin Num

EPM Signal

Board Signal

EPM7128 Pin Num

EPM Signal

1

GCLRn/in

MaxSw1_5

41

IO

2

GCLK2/in

42

GND

3

VCC

43

VCC

4

IO

MaxSw2_4

44

IO

5

IO

MaxSw1_6

45

IO

6

IO

MaxSw2_5

46

IO

7

GND

47

GND

8

IO

MaxSw2_6

48

IO

9

IO

MaxSw1_7

49

IO

10

IO

MaxSw2_7

50

IO

11

IO

MaxSw1_8 (right,lsb)

51

IO

/D1led (top,msb)

12

IO

MaxSw2_8 (right,lsb)

52

IO

13

VCC

53

VCC

14

TDI

54

IO

/D2led

15

IO

55

IO

/D3led

16

IO

56

IO

/D4led

17

IO

57

IO

/D5led

18

IO

/Maxdigit1a
(left digit)

58

IO

19

GND

59

GND

/D6led

20

IO

/Maxdigit1b

60

IO

/D7led

21

IO

/Maxdigit1c

61

IO

/D8led (bottom,lsb)

22

IO

62

TCK

23

TMS

/Maxdigit1d

63

IO

24

IO

/Maxdigit1e

64

IO

25

IO

/Maxdigit1f

65

IO

26

VCC

66

VCC

27

IO

/Maxdigit1g

67

IO

28

IO

/Maxdigit1dp

68

IO

29

IO

/Maxdigit2a
(right digit)

69

IO

30

IO

/Maxdigit2b

70

IO

31

IO

71

TDO

32

GND

72

GND

MaxSw1_1 (left,msb)

33

IO

/Maxdigit2c

73

IO

MaxSw2_1 (left,msb)

34

IO

/Maxdigit2d

74

IO

MaxSw1_2

35

IO

/Maxdigit2f

75

IO

MaxSw2_2

36

IO

/Maxdigit2e

76

IO

MaxSw1_3

37

IO

/Maxdigit2g

77

IO

38

VCC

78

VCC

MaxSw1_4

39

IO

/Maxdigit2dp

79

IO

MaxSw2_3

40

IO

/MaxPB1
(left)

80

IO

/MaxPB2
(right)

81

IO

82

GND

Osc25MHz

83

GLCK1/in

84

OE1/in


Note: /name means the signal is active LOW

This page maintained by Dr. Roger L. Haggard
Last updated: February 01, 2006