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- PLD Part Numbers
- Max7128 = EPM7128SLC84-7
- Flex10k = EPF10K20RC240-4 or EPF10K70RC240-4
- On-board jumper settings
- For Max7128 only: Set all 4 jumpers to the UP (TOP) position.
- For Flex10k20 only: Set the 4 jumpers to DOWN DOWN UP UP position respectively.
- Programming
- Compile the top-level project for the appropriate Max EPM7128SLC84-7
or Flex EPF10K20 or Flex EPF10K70 part.
- Plug the largest female connector on the power supply cable into the corresponding
socket on the Altera board.
- On the UP1/UP2 board:
- For Max, set all four jumpers (TDI, TDO, DEVICE, BOARD) to the up position.
- For Flex, set the first two jumpers (TDI, TDO) to the down position and the last two
jumpers (DEVICE, BOARD) to the up position.
- Open the top-level design project in Quartus.
- Open the Programmer from the Quartus Tools menu or click the Programmer icon.
- If it is not already setup, click HardwareSetup and Add
the Byteblaster on LPT1. Click Close.
- The Mode should say JTAG.
- Check that the proper File and Device are already listed. If not, click
AddFile and select the proper file.
- Check that the Program and Verify boxes are checked next to the file
name.
- Click the Start button to download the project configuration data
into the Max or Flex device. After several seconds, the Programmer should indicate success. The
Altera board is now running your project on the UP1/UP2 board. Hope it works!
- Board Operation in Lab
- Be careful; Minimize any handling of the board; Be gentle with the switches and buttons.
- Don't touch the voltage regulator and heat sink. IT IS HOT!
- Do NOT move boards around to different PCs; move yourself to a different PC if
there seems to be trouble with the board.
- Report any problems you have to the instructor; Be specific about which board it is and
what the problem is; put a note on the bad board so others will know.
- ALWAYS disconnect the power supply cable after use to extend the board's life.
- Problem - "Cannot find WORK directory" when compiling HDL files
- You need to have all your work in a project which is stored in a sub-directory
of the drive letter to keep Quartus happy, for example, under
z:\4110\projects\, instead of putting the
files and projects directly in drive Z:\.
- Problem - Restriction on HDL component/module names:
- Do NOT name any HDL component/module the same as any of the standard
components that already exist in the Altera library, for example
"and2" or "or4". Otherwise, Quartus will give a weird
error message until you change it.
- Problem - "Design Will Not Fit" Max7000 - Need to reduce amount of
logic used:
- Read Quartus Help about fitting a project.
- The best approaches to solving this problem follows. Note that all of these will make
the compiler run longer and the logic created will be slower, with more levels of logic
between input and output (of course, this is not much of a problem for our slow class
projects).
- Compiler - Processing - Fitter Settings - check Advanced try harder/longer compilation
fitting.
- Compiler - Assign - Global project logic synthesis - Synthesis Style = Normal, Optimize
= Area (0), Max Device Synthesis Options - check Multi-level synthesis for Max
3000/5000/7000 devices.
- Problem - "Too many I/O pins" when compiling individual components
- If you select Timing Simulation when compiling your individual components (parts of the
project), Quartus will try to fit it into an actual device that does not have enough
physical pins available, because components may have many more i/o pins than the complete
project. To avoid this, select Functional Simulation while designing and testing your
components, so Quartus does NOT try to put the component in any actual device (it just tests
the logic). Then switch to Timing Simulation to compile and perform your complete project
simulation.
- On-chip RAM/ROM Creation/Initialization (Flex10k)
- Look in the Altera help file for the RAM/ROM components, such as LPM_RAM_DQ, for more
details.
- Put your code/data in a MIF file (see Altera help on Memory
Initialization (.mif) files for the proper format). Keep your MIF file
in the same directory with all your other project design files.
- Use the Megawizard Plugin Manager to set the RAM/ROM dimensions and
other options, including the name of your MIF file.
- Your MIF file will then be automatically loaded into the RAM during
both simulation on the PC and configuration on the board.
- Problem - Big clock divider
- For sequential circuits, you may need to divide down the 25MHz system clock down to
approximately 100Hz or less for use in your circuit. If you use one huge synchronous
parallel counter, all the bits will change simultaneously, causing a huge
power pulse that
will cause the chip to malfunction. The solution is to use a small synchronous counter
with a few bits to divide the clock down to about 1MHz, then use a slower ripple counter
to divide that 1MHz clock down to the 100Hz or so that you need. The ripple counter allows
each bit to change at different times, eliminating the big power pulse and allowing the
chip to function correctly.
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