Graduate Students

Name	Degree	Year	Thesis Topic
Sara Woods	MSEE		Multiply-Accumulate Methods
Nicholas (Nick) Kurowski	MSEE	2007	Highly Scalable RC5 Cryptoprocessor Architecture
Brad Matthews	MSEE	2006	Protocol Transparent Interconnect for Network-On-Chip Applications
Sumanth Donthi	MSEE	2003	(non-thesis option)
Jie (Ellen) Chen	MSEE	2003	Detection and Extraction of Parallel Hardware during C to VHDL Translation
Vishnu Sanevelly	MSEE	2003	Implementation of a Translator from C to VHDL
Kamesh Ramani	MSEE	2002	Synthesis of Hardware from C Using C to VHDL Translation Pseudocodes as a Part of Hardware/Software Codesign
Sobha Sankaran	MSEE	2001	Hardware/Software Codesign - Efficient Algorithms for Hardware Synthesis from C to VHDL
Sunil Gopalkrishna	MSEE	2000	Alternative Arithmetic Designs for Pipelined Multiply-Accumulate Units on FPGAs
Julie Jones	MSEE	2000	Hardware-Based Methods for Maintaining Cache Coherency in a Multiple Processor System
Madhavkumar Chandran	MSEE	1999	Comparison of Sequential and Parallel Implementations of an FPGA-Based Application
Yun Sun Lee	MSEE	1999	Evaluation of Three Partitioning Methods in a Multi-FPGA System
Raghavan Venugopal	MSEE	1999	A Study of Static and Dynamic Reconfiguration Techniques in FPGA System Design
Robert Hix	MSEE	1997	A Comparison of Two VHDL Design Environments for FPGA-based Computer Arithmetic
Chris Parris	MSEE	1997	Two Implementations of a Fuzzy Variable Structure Controller
Tao Wang	Ph.D.	1996	System Level Partitioning Applied to FPGA-based Rapid Prototyping
Mason Guy, III	MSEE	1996	High Performance Dynamic Branch Prediction Architecture and VHDL Model
Greg Morton	MSEE	1995	A Practical Method for High LevelSynthesis of Combinational Logic
Leo Klaes, Jr.	MSEE	1994	A Versatile ISA Interface Design for FPGA-based Reconfigurable Systems
Royce Kimball Presley	MSEE	1994	FANN-BACK: An FPGA-based Artificial Neural Network Trained by the Backpropagation Algorithm
Samir J. Sathe	MSEE	1994	An FPGA-based Reconfigurable System as a CRT Terminal Controller